JPAD20 [Linear Systems]

PICO AMPERE DIODES; PICO安培二极管
JPAD20
型号: JPAD20
厂家: Linear Systems    Linear Systems
描述:

PICO AMPERE DIODES
PICO安培二极管

二极管 开关
文件: 总2页 (文件大小:198K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
PAD SERIES  
PICO AMPERE DIODES  
Linear Integrated Systems  
FEATURES  
DIRECT REPLACEMENT FOR SILICONIX PAD SERIES  
REVERSE BREAKDOWN VOLTAGE  
REVERSE CAPACITANCE  
PAD*  
BOTTOM VIEW  
BVR -30V  
Crss 2.0pF  
PAD1,2,5  
BOTTOM VIEW  
TO-72  
TO-72  
ABSOLUTE MAXIMUM RATINGS1  
@ 25 °C (unless otherwise stated)  
Maximum Temperatures  
2
3
K
C
2
K*  
1
A
1
A
Storage Temperature  
-65 to +150 °C  
-55 to +135 °C  
JPAD  
Operating Junction Temperature  
Maximum Power Dissipation  
Continuous Power Dissipation (PAD)  
Continuous Power Dissipation (J/SSTPAD)  
Maximum Currents  
SSTPAD  
SOT-23  
TO-92  
BOTTOM VIEW  
TOP VIEW  
1
K
K
300mW  
350mW  
3
K
1
A
2
A
2
Forward Current (PAD)  
Forward Current (J/SSTPAD)  
50mA  
10mA  
* Cathode tied to Case  
COMMON ELECTRICAL CHARACTERISTICS @ 25 °C (unless otherwise stated)  
SYMBOL  
CHARACTERISTIC  
MIN TYP MAX UNITS CONDITIONS  
ALL PAD  
ALL SSTPAD  
ALL JPAD  
-45  
-30  
-35  
Reverse Breakdown  
Voltage  
BVR  
IR = -1µA  
V
VF  
Forward Voltage  
0.8  
0.5  
1.5  
1.5  
0.8  
2
IF = 5mA  
PAD1,5  
All Others  
Crss  
Total Reverse Capacitance  
pF  
VR = -5V, f = 1MHz  
SPECIFIC ELECTRICAL CHARACTERISTICS @ 25 °C (unless otherwise stated)  
SYMBOL CHARACTERISTIC  
PAD2  
-1  
-2  
JPAD2  
SSTPAD2 UNITS CONDITIONS  
(SST/J)PAD1  
(SST/J)PAD2  
(SST/J)PAD5  
-5  
-5  
-5  
(SST/J)PAD10  
(SST/J)PAD20  
(SST/J)PAD50  
(SST/J)PAD100  
(SST/J)PAD200  
(SST/J)PAD500  
-10  
-20  
-50  
-100  
-10  
-20  
-50  
-100  
-200  
-500  
-10  
-20  
-50  
Maximum Reverse  
IR  
pA  
VR = -20V  
Leakage Current2  
Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261  
Figure 1. Operational Amplifier Protection  
Input Differential Voltage limited to 0.8V (typ) by JPADs D1 and D2. Common  
Mode Input voltage limited by JPADs D3 and D4 to ±15V.  
Figure 2. Sample and Hold Circuit  
Typical Sample and Hold circuit with clipping. JPAD diodes reduce offset  
voltages fed capacitively from the JFET switch gate.  
FIGURE 1  
FIGURE 2  
+V -V  
+V  
JPAD5  
D1  
JPAD20  
D2  
-
2N4117A  
D1  
D3  
D2  
D4  
OP-27  
+
2N4393  
ein  
CONTROL  
SIGNAL  
C
VOUT  
R
+15V -15V  
SOT-23  
TO-92  
TO-72  
0.175  
0.195  
0.130  
0.155  
Three Lead  
0.89  
1.03  
0.230  
0.37  
0.51  
DIA.  
0.045  
0.060  
1
3
2
0.195  
0.209  
DIA.  
0.175  
1.78  
2.05  
2.80  
3.04  
LS XXX  
YYWW  
0.170  
0.195  
0.030  
MAX.  
0.150  
0.115  
1.20  
1.40  
2.10  
2.64  
3 LEADS  
0.500 MIN.  
0.050  
0.89  
1.12  
0.019  
0.016  
DIA.  
0.014  
0.020  
0.016  
0.022  
0.500  
0.610  
0.085  
0.180  
0.100  
0.013  
0.100  
0.55  
1
2
DIMENSIONS IN  
MILLIMETERS  
1
2
3
0.095  
0.105  
DIMENSIONS  
IN INCHES.  
45°  
0.046  
0.036  
0.048  
0.028  
1. Absolute maximum ratings are limiting values above which serviceability may be impaired.  
2. The PAD type number denotes its maximum reverse current value in pico amperes. Devices with IR values intermediate to those shown  
are available upon request.  
Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its  
use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Linear Integrated Systems.  
Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261  

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